IDT82V3202NLG【PDF 31/117 页】IC PLL WAN EBU SGL 68-VFQFPN

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IDT82V3202

EBU WAN PLL

Functional Description

September 11, 2009

3.4

INPUT CLOCK PRE-DIVIDER

Each input clock is assigned an internal Pre-Divider. The Pre-Divider

is used to divide the clock frequency down to the DPLL required fre-

quency, which is no more than 38.88 MHz. For each input clock, the

DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.

If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is

bypassed automatically and the corresponding IN_FREQ[3:0] bits

should be set to match the input frequency; the input clock can be

inverted, as determined by the IN_2K_4K_8K_INV bit.

Each Pre-Divider consists of a DivN Divider and a Lock 8k Divider, as

shown in Figure 4.

Either the DivN Divider or the Lock 8k Divider can be used or both

can be bypassed, as determined by the DIRECT_DIV bit and the

LOCK_8K bit.

When the DivN Divider is used, the division factor setting should

observe the following order:

1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;

2. Write the lower eight bits of the division factor to the

PRE_DIVN_VALUE[7:0] bits;

3. Write the higher eight bits of the division factor to the

PRE_DIVN_VALUE[14:8] bits.

Once the division factor is set for the input clock selected by the

PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor

is set for the same input clock. The division factor is calculated as fol-

lows:

Division Factor = (the frequency of the clock input to the DivN

Divider ÷ the frequency of the DPLL required clock set by the

IN_FREQ[3:0] bits) - 1

The DivN Divider can only divide the input clock whose frequency is

lower than (

<) 155.52 MHz.

When the Lock 8k Divider is used, the input clock is divided down to

8 kHz automatically.

The Pre-Divider configuration and the division factor setting depend

on the input clock on one of the clock input pin and the DPLL required

clock. Here is an example:

The input clock on the IN2_CMOS pin is 155.52 MHz; the DPLL

required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of

clock:

Use the DivN Divider to divide the clock down to 6.48 MHz:

Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0011’;

Set the DIRECT_DIV bit in Register IN2_CMOS_CNFG to ‘1’

and the LOCK_8K bit in Register IN2_CMOS_CNFG to ‘0’;

155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the

PRE_DIVN_VALUE[14:0] bits to ‘10111’.

Figure 4. Pre-Divider for An Input Clock

Table 4: Related Bit / Register in Chapter 3.4

Bit

Register

Address (Hex)

IN_FREQ[3:0]

IN1_CMOS_CNFG, IN2_CMOS_CNFG

16, 17

DIRECT_DIV

LOCK_8K

IN_2K_4K_8K_INV

FR_SYNC_CNFG

PRE_DIV_CH_VALUE[3:0]

PRE_DIV_CH_CNFG

PRE_DIVN_VALUE[14:0]

PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG

25, 24

input clock

DivN Divider

Lock 8k Divider

Pre-Divider

DIRECT_DIV bit

LOCK_8K bit

DPLL required clock

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